Authorship：Last author   Language：Japanese   Publishing type：Research paper (research society, symposium materials, etc.)   Publisher：IEE Japan  

In this paper, a low-power capacitance-to-digital converter using Dickson charge pump is described. The proposed circuit converts capacitance to digital by transferring charges to the unknown capacitor using Dickson charge pump instead of theconventional switched-capacitor circuits requiring the operational amplifier. This circuit can achieve a very low power. This paper describes its configuration, decreasing errors, and simulated results.

Authorship：Last author   Language：Japanese   Publishing type：Research paper (research society, symposium materials, etc.)  

Authorship：Last author   Language：Japanese   Publishing type：Research paper (research society, symposium materials, etc.)   Publisher：The Institute of Electronics, Information and Communication Engineers  

Authorship：Corresponding author   Language：Japanese   Publishing type：Research paper (research society, symposium materials, etc.)   Publisher：電気学会  

3種の動作モードを有するDC-DCコンバータの制御方式をヒステリシス制御に変更し、消費電力の大きい補助電源を用いずに制御回路を動作させた場合の効率と入力電圧範囲を評価している。

Authorship：Corresponding author   Language：Japanese   Publishing type：Research paper (research society, symposium materials, etc.)   Publisher：IEE Japan  

This paper proposes a method of detecting the reciprocating propagation time of a voltage by changing the frequency of the sinusoidal input voltage input to the cable without detecting the arrival time of the voltage. Furthermore, using the proposed detection method, a measuring device for measuring the reciprocating propagation time is manufactured, and the cable length measurement accuracy is evaluated.

Authorship：Corresponding author   Language：Japanese   Publishing type：Research paper (research society, symposium materials, etc.)  

Authorship：Corresponding author   Language：Japanese   Publishing type：Research paper (research society, symposium materials, etc.)  

Authorship：Last author   Language：Japanese   Publishing type：Research paper (research society, symposium materials, etc.)  

Authorship：Last author   Language：Japanese   Publishing type：Research paper (research society, symposium materials, etc.)   Publisher：電気学会  

容量型センサは圧力、変位検知などの幅広い用途に用いられており、医療・介護分野において人体の荷重変化を検知する用途が例として挙げられる。この際に、呼吸や寝返り等の微小な体動変化を検知する必要があるが、一般的な容量・電圧変換回路では回路上のオペアンプやCMOSアナログスイッチの非理想的な特性により、変換精度が制限されてしまう。本発表では、センサの容量値をそれらの同じ誤差を含む3つの電圧値として出力し、演算することで素子の非理想的な特性の影響を軽減する信号処理回路の提案する。提案回路を0.18µm CMOSプロセスで試作集積化し、実験により評価を行った。

Language：Japanese   Publishing type：Research paper (research society, symposium materials, etc.)  

Language：Japanese   Publishing type：Research paper (research society, symposium materials, etc.)  

Authorship：Lead author   Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE  

A bio-signal amplifier whose output voltage amplitude is maximized automatically is proposed. The proposed amplifier adjusts not only the voltage gain but also the output bias voltage to maximize the output voltage amplitude. The proposed circuit is suitable for amplifying voltage signals with large spikes such as electrocardiographic signals. The proposed circuit is integrated using a 0.35 μm CMOS process, and its performances are confirmed by measurement. The measurement results show that the proposed circuit can control the output voltage amplitude by adjusting the offset and the gain.

Authorship：Last author   Language：Japanese   Publishing type：Research paper (research society, symposium materials, etc.)  

Language：Japanese   Publishing type：Research paper (research society, symposium materials, etc.)  

Authorship：Lead author   Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE  

A chopper amplifier suitable for biological signal processing in a time division manner which amplifies a plurality of input signals is proposed. Since biological signals are very low frequency signals, a chopper amplifier which has low 1/f noise is used. Furthermore, the amplifier has a highpass characteristic in order to remove the DC voltage contained in the signals obtained from the sensor. A method to remove the DC voltage accurately and quickly using DC voltage holding capacitors and voltage buffers is proposed. HSPICE simulation results show that the proposed 4-input circuit reduces the chip area by 26% and the power consumption by 29% compared to the conventional circuit.

DOI： 10.1109/ECCTD49232.2020.9218282

Authorship：Lead author   Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE  

This paper proposes a novel DC-DC converter with only one switch on the main current path of the power stage. Since the number of switches is reduced on the current path, the efficiency is improved. The wide input/output voltage range is also realized by having three types of operation modes of step-up mode, step-up/step-down mode and step-down mode. The advantages of the proposed circuit have been confirmed by theoretical analysis and simulations. Post layout simulation results show that the proposed circuit has an efficiency of more than 87% in the 0.5V to 2.5V input range with 1.8-V output voltage and 10- mA output current.

Authorship：Last author   Language：English   Publishing type：Research paper (international conference proceedings)  

In this paper, a high-accuracy switched-capacitor (SC) capacitance-to-voltage (C/V) converter is presented. The proposed circuit can greatly reduce the influences of the channel charge injection and clock feedthrough from analog switches, and the finite gain of the op-amp using three kinds of voltages. Performances of the proposed circuit are simulated by HSPICE using 0.18 m CMOS process parameters. Simulated results have demonstrated that the gain error is 0.00016 % and the maximum nonlinear error is 0.00029 % of the full scale. The conversion accuracy of 0.01 % or better can be achieved even when low-gain amplifier such as single-stage differential amplifier is used. A prototype chip was fabricated in 0.18 m CMOS process. The principles of operation of the prototype chip was confirmed by measurement results. The gain and maximum nonlinear errors are 2.34 % and 0.41 % of the full scale, respectively.

Authorship：Corresponding author   Language：Japanese   Publishing type：Research paper (scientific journal)   Publisher：IEEJ  

In this paper, an auto-zero amplifier which reduces the offset voltage and output voltage ripple caused by the non-ideal characteristics of CMOS switches is proposed. Three capacitors are used to store the compensation voltage for an internal amplifier in the proposed circuit. The capacitors hold the voltage between two input terminals of the amplifiers even if a charge injection and/or a clock feed through occur at CMOS switches. The proposed circuit reduces the output offset voltage to 43.8 % and the output voltage ripple to 42.8 % compared to the conventional circuit.

DOI： 10.1541

Authorship：Corresponding author   Language：Japanese   Publishing type：Research paper (research society, symposium materials, etc.)   Publisher：IEE Japan  

This paper proposes a novel DC-DC converter with only one switch in the main current path of the power stage. Since the number of switches is reduced in the current path, the efficiency is improved. And a wide input/output voltage range is also realized by having three types of operation modes of step-up mode, step-up/step-down mode and step-down mode. The advantages of the proposed circuit have been confirmed by theoretical analysis and simulation. The maximum efficiency of the simulation results is 95.2 %. The measurements result is also shown.

Authorship：Lead author,　Corresponding author   Language：Japanese   Publishing type：Research paper (research society, symposium materials, etc.)   Publisher：The Institute of Electronics, Information and Communication Engineers  

In this paper, we have developed an electrodeless lamp lighting circuit. The developed lighting circuit detects the current lamp state from the output current of the inverter, and automatically adjusts the frequency of the output voltage close to the resonant frequency of the load. As a result, even when the cable length is changed and the resonance frequency fluctuates, the output voltage frequency can be controlled and lit without damaging the lamp. The advantages of the developed lighting circuit have been confirmed by experiments.

Authorship：Last author   Language：Japanese   Publishing type：Research paper (research society, symposium materials, etc.)   Publisher：電気学会  

Authorship：Corresponding author   Language：English   Publishing type：Research paper (international conference proceedings)  

This paper describes how to estimate the
required number of stages of a charge pump to output the desired output voltage Vout, when the specifications such as output current Iout, capacitance of flying capacitors Ci (i=1, 2, ..., N-1) on resistance of a switch Ron, clock cycle T are given. Furthermore, The influence of Ron, Ci, and T on the output voltage is investigated. The analysis results are helpful for determining Ron, Ci, and T and improving the efficiency.

Language：Japanese   Publishing type：Research paper (research society, symposium materials, etc.)  

差動容量型センサの容量変化を、高精度にディジタル値に変換するインターフェイス回路について示す。回路は、構成素子の非理想的な特性の影響、センサ容量の温度依存性を相殺できるように構成されている。また、回路特性に影響を与えないように構成素子の低消費電力化ができるため、インターフェイスが高精度で低消費電力化が可能である。この回路の原理は差動構成でない単一型の容量型センサの信号処理にも応用できる。

Authorship：Last author   Language：Japanese   Publishing type：Research paper (research society, symposium materials, etc.)   Publisher：IEICE  

Authorship：Last author,　Corresponding author   Language：English   Publishing type：Research paper (international conference proceedings)  

Authorship：Last author   Language：Japanese   Publishing type：Research paper (research society, symposium materials, etc.)   Publisher：The Institute of Electrical Engineers of Japan  

Authorship：Last author   Language：Japanese   Publishing type：Research paper (research society, symposium materials, etc.)   Publisher：The Institute of Electrical Engineers of Japan  

Authorship：Lead author   Language：Japanese   Publishing type：Research paper (scientific journal)   Publisher：IEEJ  

A new method for realizing a zero voltage switching DC-DC converter is proposed. An additional circuit named charging and discharging circuit is introduced to realize zero voltage switching. Efficiency of a DC-DC converter is improved by using the proposed charging and discharging circuit, because variation of inductor current is suppressed. Switching timing for charging and discharging circuit are also explained. The proposed circuit is applied to a boost converter. Efficiency of the boost converter achieves 98.8%

Authorship：Corresponding author   Language：English   Publishing type：Research paper (scientific journal)   Publisher：The Institute of Electornics, Information and Communication Engeneers  

Language：English   Publishing type：Research paper (scientific journal)   Publisher：IEEE  

This paper proposes a method for modifying the functionality of conductive fabric by using different weaves on the same materials. After introducing the method, the paper demonstrates its effectiveness through an example involving fabric pressure sensors. The fabric pressure sensors in our work can alter the electrical properties of a given fabric-while using the same material in both the warp and weft direction-by changing the weaving technique at certain locations within the fabric. Conventional fabric pressure sensors require separate, location-specific outputs; every increase in the number of detection locations requires an increase in the number of detector circuit input cables. However, our fabric pressure sensors can detect location and external force via just three input-output cables.

DOI： 10.1109/TIE.2018.2885692

Authorship：Corresponding author   Language：English   Publishing type：Research paper (international conference proceedings)  

An auto-zero amplifier with a low output offsetA voltage and a small output voltage ripple is proposed. In the proposed amplifier pi-type capacitor networks are used to store the voltages which minimize the offset voltages of internal
amplifiers. The voltage between the compensation input terminals hardly varies even when switches realized by MOSFETs occur charge channel injection and/or clock feedthrough because of the pi-type capacitor networks. As a result the proposed amplifier reduces the output offset voltage and the output voltage ripple. Simulation results show that the output offset voltage and the output voltage ripple of the proposed circuit become 24.5 % and 29.0 % of those of
conventional circuit respectively.

Authorship：Last author   Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE  

A high-accuracy switched-capacitor (SC) capacitance-to-time (C/T) converter for differential capacitive sensors is presented. In the proposed circuit the propagation delays and the offset voltage of the comparator, the finite gain of the op-amp, and the channel charge injection and clock feedthrough due to analog switches have negligible effect on the accuracy of the circuit. Therefore, the design constraints of op-amp and comparator can be relaxed even for high conversion accuracy. Performances of the proposed circuit are simulated using 0.18 micrometers CMOS process parameters. Simulated results have demonstrated that the gain error is 0.0035 % and the maximum nonlinear error is about 0.015 % of the full scale and indicate that 0.1% resolution is achievable even when low-gain amplifier is used. The power consumption of the proposed circuits was 41.3 microwatts for ±0.9 V supply voltages.

DOI： 10.1109/MWSCAS.2018.8623838

Authorship：Corresponding author   Language：Japanese   Publishing type：Research paper (research society, symposium materials, etc.)   Publisher：The Institute of Electrical Engineers of Japan  

In this paper, we propose a method to remove high order passband of N pass filter with smaller scale of circuit.

Authorship：Last author   Language：Japanese   Publishing type：Research paper (research society, symposium materials, etc.)   Publisher：The Institute of Electrical Engineers of Japan  

We investigated the influence of the finite gain of the amplifier circuit in the our proposed capacity time converter. Circuit analysis and Hspice simulation results showed that the influence of the finite gain of the amplifier can be greatly reduced.

Authorship：Corresponding author   Language：Japanese   Publishing type：Research paper (research society, symposium materials, etc.)   Publisher：The Institute of Electrical Engineers of Japan  

We describe a method of realizing a soft switching of a switching DC-DC converters. The proposed circuit realizes a soft switching by just adding an auxiliary circuit to an existing circuit.

Language：English  

A switched-capacitor (SC) capacitance-to-time (C/T) converter used
for differential capacitive sensors with improved accuracy is presented
in this paper. Using three rather than two time intervals, the circuit
can remove the influences of the propagation delay of the comparator the
channel charge injection and clock feedthrough due to analog switches,
and the finite gain of the op-amp in principle. Then the proposed
circuit can perform C/T conversion with high precision. Performances of
the proposed circuit are simulated by HSPICE using 0.18 micrometers CMOS
process parameters. Simulated results have demonstrated that the gain
error is 0.00057 % and the maximum nonlinear error is about 0.0015 % of
the full scale. It is also shown that a high-accuracy C/T converter can
be realized even when a low-gain amplifier is used. The circuit can
relax the restriction on the design of a comparator and an op-amp even
for high conversion accuracy. As a result, the power consumption of the
circuits can be also reduced.

Authorship：Corresponding author   Language：Japanese   Publishing type：Research paper (research society, symposium materials, etc.)   Publisher：電気学会  

オートゼロ技術を用いた演算増幅器において出力電圧オフセットおよび出力電圧オフセットを低減する手法を２種類示し，それらの効果を比較していいる。

Language：Japanese   Publishing type：Research paper (research society, symposium materials, etc.)   Publisher：情報処理学会  

導電性織物を使用した圧力センサは，電子デバイスと布製品が一体化したe-テキスタイルの一種であり，生体信号の測定や電子デバイスへの入力インタフェースとして応用されている．導電性織物の場合，絶縁体によって被膜された垂直方向及び水平方向の導電性糸の間の静電容量の変化を検出することで圧力の大きさや位置を検出するが，検出位置が増えるごとに検出回路の入出力チャンネルの数も増加する問題がある．本研究では，織り方が異なる3 枚の織物を組み合わせた加圧位置検出織物を提案し，実際に作製した織物から入出力3 チャンネルで位置と外力の大きさが検出可能かを検証する．

Authorship：Corresponding author   Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE  

An implementation of a differential N-path filter with sampling computation design method is proposed. It offers the ability to eliminate the harmonic passbands of the clock frequency. On top of that, the proposed method enables the scale of the whole filter to be reduced by approximately half for easier realization. By using the proposed method, previous work involving a 8-path filter can be reduced to 5-path, which reduces the scale of the circuit and at the same time has the performance
of a 10-path filter if designed with the method proposed by previous work. An example of differential 7-path filter using the same proposed design method is also stated in comparison of the differential 5-path filter. The differential 7-path filter offers the ability to eliminate all the passbands below 10 times the clock
frequency with a tradeoff of a slight increase of circuit scale.

Language：Japanese   Publishing type：Research paper (research society, symposium materials, etc.)   Publisher：IEE Japan  

In this study, an auto-zero amplifier which reduces the effect of the non-ideal characteristics of CMOS switches is proposed. Three capacitors are used to store the compensation voltage for an internal amplifier in the proposed circuit. The capacitors hold the voltage between two input terminals of the amplifiers even if a charge injection and/or a clock feed through occur at CMOS switches. The proposed circuit reduces the output offset voltage to 16.4% and the output voltage ripple to 12.3% when compared to the conventional circuit.

Language：Japanese   Publishing type：Research paper (research society, symposium materials, etc.)   Publisher：IEE Japan  

To reduce the number of I/O channels between circuit and conductive fabric, we propose a pressure position
sensing fabric consisting of three sheets in different patterns. The fabric detects pressure and position with th
-ree I/O channels only.

Authorship：Lead author   Language：Japanese   Publishing type：Research paper (scientific journal)   Publisher：IEEJ  

Dynamic voltage scaling (DVS) is one of the most effective power reduction techniques for a digital VLSI circuit.
A fully integrated DC-DC converter is indispensable to achieve DVS. There is a trade-off between the output
voltage ripple of a fully integrated DC-DC converter and its chip area. This paper proposes a design methodology
which minimize the total chip area of a fully integrated multi-phase converter with an acceptable voltage ripple. The
proposed design methodology reveals an equation of the optimum inductance and capacitance. Validity of the
proposed design methodology is confirmed by Hspice simulations. The simulation results of a design example show
that the output voltage ripple of a multi-phase converter with the optimum inductance and capacitance derived by
the proposed design methodology is kept within a requirement value.

Authorship：Lead author,　Corresponding author   Language：Japanese   Publishing type：Research paper (research society, symposium materials, etc.)  

Language：English   Publishing type：Research paper (scientific journal)   Publisher：IEEE  

Burst mode control techniques have been studied for LLC resonant dc-dc converters to improve power conversion efficiencies at light load conditions. However, there are not many studies about how to detect the load conditions at burst mode not even at normal mode, at the primary side of LLC resonant dc-dc converters. In this paper, we propose and implement a lossless load detection technique for normal and burst modes by a novel average input current sensing method at the primary side of LLC resonant converters. Detailed theoretical analysis at normal and burst modes is presented and a load detection circuit is proposed with the consideration of integrated circuits. To verify the analysis, an LLC resonant offline converter with 400 V input and 16 V/10 A output is simulated using PSIM and a prototype board is built. The experimental results show that the proposed load detection technique is valid and practical. As a result, an automatic burst mode control for LLC resonant converters at light load conditions is realized with the proposed average input current sensing method.

Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE  

A precise overload protection is able to improve
the thermal design of power supply systems. However, as for
LLC resonant off-line converters, there are not many studies
about how to detect the load conditions at the primary side of the
converters which is important to realize the precise overload
protection. In this paper, we implement a lossless and precise
load detection technique by a novel average input current sensing
method to achieve the precise overload protection. Detailed
theoretical analysis is presented with statistical analysis on
overload conditions. To verify the analysis, an LLC resonant offline
converter with 400V input and 16V/10A output is simulated
using PSIM and a prototype board is built. The theoretical and
experimental results show that the precise overload protection is
realized based on the novel load detection technique. As a result,
the thermal design of the LLC resonant off-line converters is
improved.

Authorship：Corresponding author   Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE  

An implementation of a differential N-path filter with sampling computation design method is proposed. It offers the ability to eliminate the harmonic
passbands of the clock frequency. On top of that, the proposed method enables the scale of the whole filter to be reduced by approximately half for
easier realization. By using the proposed method, previous work involving a 8-path filter can be reduced to 5-path, which reduces the scale of the circuit
and at the same time has the performance of a 10-path filter if designed with the method proposed by previous work. An example of differential 7-path
filter using the same proposed design method is also stated in comparison of the differential 5-path filter. The differential 7-path filter offers the ability to
eliminate all the passbands below 10 times the clock frequency with a tradeoff of a slight increase of circuit scale.

Authorship：Last author   Language：Japanese   Publishing type：Research paper (research society, symposium materials, etc.)   Publisher：IEE Japan  

Authorship：Corresponding author   Language：Japanese   Publishing type：Research paper (research society, symposium materials, etc.)   Publisher：IEE Japan  

Authorship：Corresponding author   Language：Japanese   Publishing type：Research paper (research society, symposium materials, etc.)   Publisher：The Institute of Electrical Engineers of Japan  

Authorship：Last author   Language：Japanese   Publishing type：Research paper (research society, symposium materials, etc.)   Publisher：IEE Japan  

Authorship：Lead author,　Corresponding author   Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE  

A cascaded differential 20-path and 3-path filter which realizes a more than 20 dB stopband rejection and harmonic rejection ability is proposed. Compared to a differential N-path filters with a passive low-pass filter connected between the signal source and the filter itself, the proposed cascaded N-path filter provides better flexibility in tuning and narrower full width half maximum (FWHM) value for higher frequency selectivity. The first stage 20-path filter which acts as a tunable low frequency band-pass filter operates at a frequency of fs2/3 (fs2 = switching frequency of second stage N-path filter) attenuating the undesirable high frequency signals. The second stage 3-path filter then filters off the remaining standards providing sufficient stopband rejection for the whole system. The different operating frequencies for both stages provides a harmonic rejection ability as the high frequency components causing the harmonic folding of fs2 are first removed before passing through the second stage N-path filter for a desirable standard.

Authorship：Corresponding author   Language：Japanese   Publishing type：Research paper (research society, symposium materials, etc.)   Publisher：IEE Japan  

The voltage across the parasitic capacitor of the piezoelectric transducer is flipped each half cycle by adopting the bias-flip rectifier to obtain a higher output power for the power supply. A control circuit managing the switches in the bias-flip rectifier is proposed and designed to adapt to piezoelectric transducers vibrating at low frequencies. Unwanted switching errors caused by frequency fluctuation can be overcome by either inserting a resistor as a voltage divider or designing a hysteresis band for the comparator used. A result stating the proposed circuit could harvest 1.4 times more power when compared to a general rectifier circuit.

Authorship：Lead author,　Corresponding author   Language：Japanese   Publishing type：Research paper (scientific journal)   Publisher：IEE Japan  

Authorship：Corresponding author   Language：Japanese  

Authorship：Corresponding author   Language：Japanese   Publishing type：Research paper (research society, symposium materials, etc.)  

Authorship：Lead author   Language：English   Publishing type：Research paper (international conference proceedings)  

Authorship：Lead author,　Corresponding author   Language：Japanese  

Authorship：Corresponding author   Language：Japanese  

Language：Japanese  

Authorship：Corresponding author   Language：Japanese   Publishing type：Research paper (research society, symposium materials, etc.)  

Authorship：Lead author,　Corresponding author   Language：Japanese   Publishing type：Research paper (scientific journal)  

Language：Japanese  

Authorship：Lead author   Language：English   Publishing type：Research paper (international conference proceedings)  

Language：Japanese   Publishing type：Research paper (research society, symposium materials, etc.)  

Language：Japanese   Publishing type：Research paper (research society, symposium materials, etc.)  

Authorship：Corresponding author   Language：Japanese   Publishing type：Research paper (research society, symposium materials, etc.)  

Language：Japanese   Publishing type：Research paper (research society, symposium materials, etc.)  

Language：Japanese   Publishing type：Research paper (international conference proceedings)  

Language：English   Publishing type：Research paper (international conference proceedings)  

Language：English   Publishing type：Research paper (international conference proceedings)  

Language：Japanese   Publishing type：Research paper (research society, symposium materials, etc.)  

Authorship：Corresponding author   Language：Japanese   Publishing type：Research paper (research society, symposium materials, etc.)  

Authorship：Corresponding author   Language：Japanese   Publishing type：Research paper (research society, symposium materials, etc.)  

Authorship：Corresponding author   Language：Japanese   Publishing type：Research paper (research society, symposium materials, etc.)  

Authorship：Lead author,　Corresponding author   Language：English   Publishing type：Research paper (scientific journal)  

Language：Japanese   Publishing type：Research paper (scientific journal)  

Authorship：Lead author,　Corresponding author   Language：English   Publishing type：Research paper (international conference proceedings)  

This paper proposes a novel buck converter with
fast output voltage transition. The proposed buck converter
keeps on increasing its inductor current during transition of
the output voltage. Increasing the inductor current is effective
to minimize the transition time of the output voltage because
an output capacitor must be charged or discharged by the
inductor current when its output voltage is changing. On the other
hand, the proposed operation yields excess inductor current when
the transition has been completed. The excess current causes
overshoot and undershoot of the output voltage. To reduce this
overshoot and undershoot the excess current is returned to the
power supply and its power is recovered. The inductor current is
reduced rapidly by the current regeneration. The buck converter
can return to the normal operation quickly. A new current path
used for the current regeneration is realized by a few switches.
Performance of the proposed buck converter is confirmed by
computer simulations. The simulation results show that step-up
transition time of the proposed converter is about 83 % of that
of conventional circuit.

Language：Japanese   Publishing type：Research paper (international conference proceedings)  

This paper presents that analysis of flash A/D
converter gain effect in delta-sigma modulator and proposes new
power dissipation technique by using the flash A/D converter’s
gain. At first, flash A/D converter model which consists of gain
block and quantization noise summation block is cleared by
using input-output characteristics. The slope of flash’s inputoutput
characteristic means equivalent gain and designers can
arbitrarily assign the equivalent gain for suitable value by
designing the threshold voltages. Next, it is shown that coefficient
of integrator decides power dissipation of opamp in the integrator
regardless of continuous time / discrete time types. In this paper’s
analysis, small coefficient of integrator can reduce opamp desired
specifications. In order to reduce power dissipation of opamp, we
propose a technique that integrator coefficient can be relaxed by
using flash A/D converter gain. The effect of this technique is
confirmed by MATLAB/Simulink system simulations.

Authorship：Corresponding author   Language：Japanese   Publishing type：Research paper (research society, symposium materials, etc.)  

Authorship：Lead author,　Corresponding author   Language：Japanese   Publishing type：Research paper (research society, symposium materials, etc.)  

Authorship：Corresponding author   Language：Japanese   Publishing type：Research paper (research society, symposium materials, etc.)  

Language：Japanese   Publishing type：Research paper (research society, symposium materials, etc.)   Publisher：電子情報通信学会  

Language：Japanese   Publishing type：Research paper (research society, symposium materials, etc.)  

Authorship：Lead author   Language：English   Publishing type：Research paper (scientific journal)  

Authorship：Lead author,　Corresponding author   Language：Japanese   Publishing type：Research paper (research society, symposium materials, etc.)  

Authorship：Lead author   Language：English   Publishing type：Research paper (international conference proceedings)  

Authorship：Corresponding author   Language：Japanese   Publishing type：Research paper (scientific journal)  

Authorship：Corresponding author   Language：Japanese   Publishing type：Research paper (research society, symposium materials, etc.)  

Authorship：Lead author,　Corresponding author   Language：English   Publishing type：Research paper (international conference proceedings)  

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Language：English   Publishing type：Research paper (international conference proceedings)  

Authorship：Lead author   Language：Japanese   Publishing type：Research paper (research society, symposium materials, etc.)  

Language：English   Publishing type：Research paper (international conference proceedings)  

Language：Japanese   Publishing type：Research paper (research society, symposium materials, etc.)  

Language：Japanese   Publishing type：Research paper (research society, symposium materials, etc.)  

Authorship：Lead author   Language：English   Publishing type：Research paper (international conference proceedings)  

Authorship：Lead author   Language：English  

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Applicant：東京工業大学　豊橋技術科学大学

Application no：2005-175052  Date applied：2005.6

Patent/Registration no：2006-352441 

Country of applicant：Domestic  

Applicant：株式会社半導体理工学研究センター

Application no：2004-95013  Date applied：2004.3

Patent/Registration no：2005-286516 

Country of applicant：Foreign country  

Applicant：株式会社半導体理工学研究センター

Application no：2001-319760  Date applied：2001.10

Patent/Registration no：2003-124755 

Country of applicant：Foreign country  

Multi-Path Analog Circuits Robust to Digital Substrate Noise

Systematic design of MOSFET-C Impedance Simulation Circuits Based on GIC

同一チャネルMOSFETのみをVCCSとして用いたRail-to－Rail OTA

高線形MOSアナログ集積回路の構成

Audience： High school students

（活動の内容）
システムLSI内の雑音の影響を低減するための技術を調査研究する。
（開催回数）
4